Parallella 2.0 Design Specifications

[patc]

Probably too late to provide inputs but I got my Parallella a week ago and I missed a JTAG connector.

I mean I discovered the Zynq a couple of months ago and ordered the Avnet MicroZed board. I must say it was instant love with the Zynq!

Then I found the Parallella which is much cheaper and it's got the Epiphany chip on top. Frankly speaking, right now I'm not into Epiphany but this is something I'll definitely take a closer look at later on.

I understand that Parallella's focus is parallel computing but I guess there are folks out there who are looking for a cheaper alternative to the MicroZed and the ZedBoard and I think a dedicated JTAG connector on the Parallella would be a big plus.

Then something like PMOD connector/reset button/boot mode jumper would certainly be nice... just my 2 cts.

[IDP]

There are many applications which don't need the Epiphany chip even if this was the main reason for the Parallella development.
If you make a BGA package which only reroutes the FPGA IOs to the North and South connector you will cover a broader market with the board and increase the production volume.
if you removing the second USB but are leaving the micro USB connector for 5V power then consider to place FTDI USB-UART chip instead for the 3 pin UART connector , but don't connect the global reset to the chip so the host keeps the connection during a reboot (which is not the case on the MicroZed).
JTAG connector is a must for proper FPGA development. if you don't have the space for the 14 pin XILINX connector place a micro connector at the board edge and sell a separate adapter.

[9600]

[timpart]

[marek]

[max333]

Was this 2.0 revision the batch that was sent at the end of July? It seems too soon.

If 2.0 is a completely new revision, will the epiphany processor have more than 16 cores and larger memory per core? This thread only talks about the board and not the epiphany processor.

Would this be available in a few months? or a few years?

[aolofsson]

Parallella 2.0 has not been shipped and will not ship this year. We are looking for more use cases and feedback before making some of the design decisions.

[Bren]

I would give a +1 for the jtag. I would use a compatible header for the digilentinc connector, as it's just a 100 mil single row and you can also use it with the standard xilinx programmer. see data sheet.

http://www.digilentinc.com/Data/Product ... HS1_rm.pdf

I would also for the production run remove all the capacitor and resistor makings on the board as the user doesn't need this info. You can use the extra space to make the "User" marking clear, for example the Jumpers, board version, mark on the bottom for the connectors GPIO, Power, north / south. I think you need to add an indicator which pin is 1 and 2 on the expansion connectors to clear up any miss information.

I would prefer that you didn't add items that increased the price, I personally think version 2 should be used to refine what is already there and maybe try and decrease the cost by optimising BOM count.

Keep up the good work.

[Grumpy Old Coot]

Warning: Clueless Newbie Ahead, no Parallella to play with... Yet.

Going off the photos:
- Basic board design: That plate heatsink on the Embedded definitely needs a fan. 5v@2A is a lot of heat for anything of this form factor.
- HDMI mini/full size: I can always buy an adapter, but if you are looking for board space, I thought I saw a Foxconn part that was a HDMI mini/USB mini in an "on edge" stack (90 degree?). There isn't room underneath to move them, unless there's a magical way to shrink that MicroSD_card.
- Rearranging the two jumpers would help space wise.

Can't think of anything else. I just know I keep looking at those N/S E-Link connectors and wondering how to connect ADCs and DACs to them.

[bandan]