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Parallella Community • View topic - Peripherals and Interfaces of the SoC

Peripherals and Interfaces of the SoC

Any technical questions about the Epiphany chip and Parallella HW Platform.

Moderator: aolofsson

Peripherals and Interfaces of the SoC

Postby DEPC » Tue Dec 25, 2012 2:53 am

I have been looking at the datasheet of the Zynq SoC and just wondering without increasing complexity, if you are only planing on populating one of the Ethernet and USB ports each, is it possible to have the spare Ethernet and USB ports go to the expansion GPIO headers or if not could there be access to them via solder pads.

I know we don't wont to make this 1st Dev board complex just wondering what was the aim is with the Interfaces.

Thanks
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Re: Peripherals and Interfaces of the SoC

Postby jeinstei » Wed Dec 26, 2012 12:48 pm

That's a great question. I'm a bit curious myself. We work with Freescale Tower kits regularly, and they did a great job of providing a header that provides access to almost every pin, regardless of what other peripherals are hanging off it.

Just curious, but where is the Zynq SoC datasheet? Does Zynq provide an IDE, or do we need to use libraries and integrate them?
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Re: Peripherals and Interfaces of the SoC

Postby fmotta » Wed Dec 26, 2012 9:37 pm

I have requested I/O info a few times and still have none.

It'd be nice to determine what applications I can apply this toward based on what connectivity I will get...

It'd be a pain to have to use Linux mmap I/O as the only I/O for data... that'd be be quite a pain.
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Re: Peripherals and Interfaces of the SoC

Postby DEPC » Thu Dec 27, 2012 6:00 am

The datasheet I found is this one http://www.xilinx.com/support/documenta ... erview.pdf

Coming to think off it I'm hoping that I got the right SoC.
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Re: Peripherals and Interfaces of the SoC

Postby fmotta » Thu Dec 27, 2012 4:58 pm

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Re: Peripherals and Interfaces of the SoC

Postby DEPC » Fri Dec 28, 2012 11:56 pm

Cool thanks, I have done very limited amount of VHDL coding for FPGA's but I'm just not to familiar with the hole physical CPU's surrounded by the gate array logic, if the Ports are limited to very specific pins or they can be routed to be more easily accessed.

EDIT: Found the MIO table in the ZYNQ technical reference manual and answering my own original question, seeing that ware using the ZYNQ7010 (probably the CLG225) it only supports one Ethernet and one USB.
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Re: Peripherals and Interfaces of the SoC

Postby aolofsson » Mon Jan 07, 2013 2:28 am

Slight correction, it supports 1 ETH and 2 USBs. It's the zynq7010 in the 400 ball package.
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Re: Peripherals and Interfaces of the SoC

Postby DEPC » Mon Jan 07, 2013 7:17 am

Awesome thanks. That cleared it up for me.
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posting

Postby Naveed123 » Tue Jun 04, 2013 9:58 am

:twisted: :twisted: this is very very possible to have the spare Ethernet and USB ports go to the expansion GPIO headers or if not could there be access to them via solder pads.
:ugeek: :ugeek:
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