AXI clocked at 40 MHz !?!?!

[tnt]

I was just looking at the HDL and I stumbled onto the fact that both the master and slave AXI interface to the ARM core are clocked at 40 MHz ... which seems insanely low !

So _why_ ?!? Can't meet timing ? That'd be a shame ...

[aolofsson]

We're just trying to "First make it right, then make it fast." The zynq FPGA logic (7010 and 7020) is manufactured in a low power process so it's not the fastest (when compared to the 7045 for example). Still, I am sure we will be able to rev up the logic speed once we get the time to do RTL optimization and push the tools.

Andreas