Interconnecting and powering Parallella

[ticso]

I intend to place 3 Boards onto a board for 6HE 19" card carrier.
The Ethernet ports will be headed to the outside, but supplying them via barrel plug sounds silly, when 3 are placed onto a single board and I have the option to drive power through a backplane.
Is it possible to power the boards using the IO connectors?
SYS_5P0V seems to be the only possible option, but it is marked as output only.

Using PEC_NORTH/SOUTH is it possible to interconnect the parallella boards?
I like to use all 3 ZYNQ, but since they are on the same board interconnecting the epiphany sounds like a good idea.

How is the addressing done?
Each epiphany has a specific position in global matrix and specific addresses are routed via one of the 4 links into the next chip.
But a parallella has 1G RAM.
Is this RAM completely mapped into epiphany address space?
If yes how is it done?
With an E16 normally via external link I would expect only up to 1/16th of complete 4G space in that east/west direction.
If such an elink can address more than it's logical space in matrix, can I map all 3x 1G RAM into 4G epiphany space?

[aolofsson]

[timpart]

@aolofsson did you implement @sundance's suggestion of using the mounting holes to supply power to the boards? There is no mention of this in the preliminary board spec, but I notice in one of the photos of the prototype boards they are stacked using metal spacers.

I'm also a bit puzzled by your reply about the RAM usage. When the boards are connected together can they only use the external RAM on one of the boards? I still haven't worked out how each chip knows which elink to use to reach the outside world.

Thanks,
Tim

[aolofsson]

Tim,

Yes, we did implement Sundance's suggestion of using one of the mounting holes for power but we hedged our bet (based on the controversy around the suggestion) and left the hole floating by default. To enable this feature, the user would need to short out two fairly large pads. The Parallella board spec will be published this week!

In terms of the shared memory space in the multi Parallella configuration, Epiphany cores will essentially become masters on all the AXI buses on all the Zynq chips. However, due to the east/west/north/south routing restrictions of thh Epiphany, getting to every corner of the memory map becomes tricky. We are still looking into whether all the cores will be able to directly access the DRAM on all boards or whether we will need some "proxy" Epiphany core on each Parallella board that will allow routing to be done north/south between the different boards and then east/west between the Epiphany and the DRAM on that board. I will put together a figure...

Thanks,
Andreas

[ticso]

Ah - that's the trick.
Writes to all addresses travel east/west first, so they go out east or west of the chip no matter what north/south position the address has, unless it is at same east/west position as the writing chip.
That way you can have a full 1G mapping into epiphany address space - but it is not continuous as each row only has 64MByte including some space for on-chip columns.
However that way it seems impossible to reach any other (non epiphany) memory location connected east or west on another chip.

Not sure if it matters that much as writing back from epiphany has to be smarter than just issuing a bulk request into SDRAM space.
I considered running cores in ping pong buffer configuration.
ARM DMA writes a block into any free core.
A finished core DMA writes result block into SDRAM.
However if more than one core is writing a block, data gets interleaved and may trash SDRAM page opening reducing memory bandwidth.
Even if this won't happen both writes will finish latter, while one block could have been finished in half time and only the second needs to be waited full time.
Bulk writing from a core into SDRAM should be done scheduled by one instance.
This way there is no additional page trashing - beside concurrency with ARM side activity and bandwidth isn't shared.

[hewsmike]

FWIW : I have just constructed and I am now testing a for the Parallella board. A fairly straight forward design with fusing ( nominal values at present ) and separate supply to the power meter. The idea is to log power consumption to PC software while computing and also have some voltage and current protection. This is for those who don't want to use USB power to the board, but take advantage of the 2.1mm barrel connector jack input.

Cheers, Mike.