by nizar » Thu Dec 19, 2013 2:02 pm
Hi Andrew,
thank you very much for your reply,
for my project right now important is computing, we knew the elink has 2gb/s for each direction in single core.
as i'm going to split data process between many chip, at the first step this enough for me even slower until adapteva try to make something similair or more better like TileraPro64 , they has dedicated DDR 4 of them this reduce time to access for SRAM.
But andrew if possible I have a question I'm going to use 64 chipset in single board, and going to use 4 elink port (e,w,n,s)
as we know it has 4bits for col and 4 bits for rows, could u sugguest the best way to orgonize this chipset, my solution right now going to use as follow
4X4 in single board, and 4x16 boards.
to avoid latency of frame analyse I decide to use arbitrer processor quadcore is like imaging co processor,
and all chipset going to be use like 3D matrix multi, 2D, to calculate distance, object size all in rela time.
best regards