I'm not exactly sure what people are still discussing here ...
AFAICT from the history of this thread, the issue has been diagnosed. The ULPI PHY sometimes comes out of reset in a weird state where it's not responsive despite being provided with a clean reset pulse. The design used the Xilinx recommended PHY and is connected properly so it _should_ work. Obviously it doesn't (or not reliably for some people) so the failure lies either with Xilinx's zynq doing weird stuff on the pin pre-boot or with the PHY behaving strangely sometimes, but at this point it really doesn't matter all that much.
Given that none of this is under software control, I don't see how a firmware upgrade or FPGA bitstream upgrade alone would do anything. The only solution seems to be to extend the reset pulse of the PHY about 100ms longer than the one from the PS (so that the FSBL has had time to properly configure the pins) and this will require some hw mod. The question is how to achieve that in the easiest way possible.