Vivado Support?

[DeanoC]

Any idea, when Vivado support might become available? Loading up in the Planahead in Vivado doesn't work unfortunately (can't find the system module) and the timing will need converting.

But it supports SystemVerilog for synthesis which would be nice for more complex PL parts.

Not asking for a date, just a rough idea would be nice, as you've mentioned moving to Vivado is the plan in a few posts.

[FHuettig]

Hi,

I am actively working on this, but it's never as simple as I want it to be. I found out the hard way that simply updating everything to version 14.7 in the PlanAhead flow requires new versions of u-boot, the fsbl, the ADI/Xilinx modules, all the way up to the Linux kernel. So we are doing the "simple" port to Vivado along with all the other updates necessary, and will have to release a new Ubuntu image to support it at the same time. I expect this to take a few weeks before we've gotten everything tested thoroughly. If I could simply port the projects we've got to the new tools I would.

-Fred

[DeanoC]

Completely understand how difficult such a 'simple' thing is.

If you need someone to test some of the things let me know.

Thanks alot for working on it

[bedoustani]

[FHuettig]

[SiDe]

Hello FHuettig,

I would be much interested in the design under Vivado, even if it is not completed yet. My purpose is not to use the Epiphany chip, but just to create a project using the Ethernet port, the HDMI, and the DDR.

I think interfacing HDMI and Ethernet will be fine (same as with the Zedboard) but I have some doubts about the DDR.
Can I ask you if the problems your encounter while porting the design are due to interfaces, or IPs migration?

Thank you a lot,
Simon D.

[Bren]

Hi I would also ask if you could release what you have now. I'm in the process of porting a zedboard project to your board that only uses the ethernet controller and the UART (ethernet would be fine for now). But we can't get linux to boot. We look at your ISE project and our vivda project and see why this should be. Is it due to the RAM? Also when you ported from zedboard to your original prototype what did you change to get a ethernet and linux to work?

Thanks

Bren

[Seb79]

Hi all,

is there any update when?

Thanks,
Seb

[bedoustani]

Hi,
For the FPGA implementation of the Parallella board (Hedless) with Vivado do the following steps:
1-Read all immigration steps from ISE to Vivado (Zynq configuration, timing constraints, IO constraints, etc. ) and apply them. Be careful about constraint specially IO constraints.

2-Generate the eLINK IP in Vivado using hdl source files.

3- Generate an IP for the GPIO_EMIO and another IP for the Parallella system reset using hdl source files.

4-Put your own IP in the project that you want to have in Parallella Board.

When you try to generate bitstream the Implementation failed with some timing violation. Also, in the generating bitstream file, you will got the following error:
"[Drc 23-20] Rule violation (LUTLP-1) Combinatorial Loop - 41 LUT cells form a combinatorial loop.........."

Timing error:
The timing problem is because BUFG maximum frequency for the xc7z020clg400-1 is "464Mhz" and MMCM generate 600 Mhz. . You can easily bypass this problem since it is working for 600 Mhz. (If you repeat the implementation for the "xc7z020clg400-2" which has BUFG maximum frequency of "628Mhz" you will not have this timing problem.)

Rule violation problem:
I discussed the Rule violation problem with Fred and he confirms that the loops Vivado found in the code are real. He also confirm that the loops are "safe" in that the specific logic does not have any way to latch or oscillate, but Vivado will flag them because such loops are a bad idea in general.
You can bypass this problem too.

Then you can complete the FPGA compilation.

[shaskey]

Hi Bedoustani,

Does the Vivado version of the project you have managed to build work with the standard Linux and U-boot for the parallella?

Thanks