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JTAG POWER_PEC + Vivado Question
Posted:
Mon Sep 15, 2014 3:52 pm
by Michael19
If for example, I managed to make a breakout board for the POWER_PEC on the Parallella Z7020 board and connected the JTAG to say a Xilinx Programming Cable or equivalent such as Digilent's JTAG HS1, would it be possible to program to the Parallella using the Vivado Design Suite?
Re: JTAG POWER_PEC + Vivado Question
Posted:
Mon Sep 15, 2014 7:14 pm
by patc
If you mean making your own standalone PL/PS design, yes no problems because that's something I'm doing probably 40 or 50 times a day (with HS2).
QSPI is fine and for DDR you need to setup PL as below:
Re: JTAG POWER_PEC + Vivado Question
Posted:
Tue Sep 16, 2014 5:14 am
by Michael19
Yes I do mean making my standalone PL/PS design. So with digilent HS2 I just connect it to the JTAG module, I don't have to connect the HS2 to the QSPI? I don't mind it being albeit slow so QSPI would be fine, but just to be sure if I save it on the QSPI I could use the design without a computer.
Re: JTAG POWER_PEC + Vivado Question
Posted:
Wed Dec 17, 2014 3:51 pm
by Transcendental
Should the JTAG HS3 Programming Cable be used in conjunction with the Porcupine breakout board's JTAG header and Xilinx's Vivado 2014.x ?
See:
http://www.digilentinc.com/Products/Det ... d=JTAG-HS3http://www.digilentinc.com/Data/Product ... HS3_RM.pdfIn the latter document, the section "Xilinx Zynq-7000 and SoC Support" specifies the usage and requirements involving pin 14. What are the ramifications here, if any, regarding the Porcupine board?
Re: JTAG POWER_PEC + Vivado Question
Posted:
Wed Dec 17, 2014 4:30 pm
by FHuettig
The porcupine does not connect pin 14 on the JTAG connector.
I've only used the Xilinx Platform Cable USB-II, but have not had any problems using xmd for the limited work I've done through the Porcupine's JTAG to the Zynq PS. Most of my work has been programming the PL and running ChipScope, which has worked well but does not require pin 14, but I have used xmd to load u-boot and re-flash boards.
I would give it a try as-is, and if the tools report a problem being unable to reset the PS you can jumper the reset signal from pin 6 of J2 to pin 14 of J1 on the Porcupine.
-Fred
Re: JTAG POWER_PEC + Vivado Question
Posted:
Mon Dec 29, 2014 8:26 pm
by steddyman
Trying to find an inexpensive JTAG programmer that will work with vivaldo and ise. Would love to know what Pat is using.
The USB cable II costs nearly £300 in the uk which is twice the cost of the parallella board!
The hs3 cable mentioned above is a much more reasonable £50. Also spotted this on eBay, but not sure if it could do the job or not:
http://www.ebay.com/itm/280959075692
Re: JTAG POWER_PEC + Vivado Question
Posted:
Tue Dec 30, 2014 11:13 pm
by patc
That's the one:
Hope this helps.
Re: JTAG POWER_PEC + Vivado Question
Posted:
Tue Dec 30, 2014 11:55 pm
by steddyman
Perfect thanks pat.
Is it easy to create a Vivado template project matching the existing Parallella design to then customise for all projects, but supporting all existing on board components?
Re: JTAG POWER_PEC + Vivado Question
Posted:
Wed Dec 31, 2014 2:02 pm
by patc
You're welcome.
If I'm not mistaking please note that the Parallella design is not yet available under Vivado.
Personally so far I've only been using the Zynq with DDR, QSPI, SPI, SDHC, serial port and GPIOs under Vivado so I can confirm I didn't find any particular problem with those components (although being a beginner with FPGA, I can't recall how many times during the past months I've hit the "Total Despair" state
)
Re: JTAG POWER_PEC + Vivado Question
Posted:
Wed Dec 31, 2014 11:12 pm
by steddyman
Thanks again Pat
I'm not too concerned with having the Epithany chip working, but I would like to make use of the hdmi video, sound, USB keyboard along with the memory and flash. I'm not too familiar with Vivado but noticed the board wasn't listed under new project setup, so wasn't sure how to get most options enabled and configured.