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Parallella Community • View topic - Epiphany FPGA communication.
Page 1 of 2

Epiphany FPGA communication.

PostPosted: Thu Sep 25, 2014 6:15 pm
by AndyC
Hi Guys,

What's the recommended way of going about this?

Cheers

Andy

Re: Epiphany FPGA communication.

PostPosted: Thu Sep 25, 2014 9:37 pm
by FHuettig
Hi Andy,

Because the AXI-eLink interface logic is quite involved, and I don't expect that you want to give up control of the Epiphany from the Arm CPUs, I think the easiest way would be to use one of the unused AXI slave interfaces, either GP or HP, to route your read/write requests to the Epiphany interface. I expect that you can do this without taking any bandwidth away from non-Epiphany transactions inside the PS, the PS interconnect block should (I hope) be able to handle concurrent transactions between independent ports.

If you need the Epiphany to write to / read from your logic you'll have to use a master AXI port and assign it an address range that you then use on the Epiphany.

I do have it on my list to implement streaming interfaces to/from the FPGA fabric from/to the Epiphany, with either the Arm or Epiphany setting up a list of descriptors to determine how the data is distributed/gathered, but it will be a while before that happens.

-Fred

Re: Epiphany FPGA communication.

PostPosted: Fri Sep 26, 2014 6:31 am
by AndyC
Hi Fred,

Thanks very much for the pointers.

Looks like I need a master AXI port, are there any restrictions on access to memory locations from the Epiphany or can it access anything?

Cheers

Andy

Re: Epiphany FPGA communication.

PostPosted: Fri Sep 26, 2014 8:24 am
by AndyC
Hi Fred,

My hopeful first attempt at just writing to the 'correct' AXI address from the Epiphany caused the parallella to hang!

So I am obviously being a bit naive, how do you map an AXI address say 0x7AA00000 to the Epiphany?

Thanks for any help.

Andy

Re: Epiphany FPGA communication.

PostPosted: Tue Sep 30, 2014 6:37 am
by AndyC
Anyone got any idea of how to do this?

I tried to map the AXI registers into the shared ram address range and XPS doesn't like this at all.

I'm stumped here.

Cheers

Andy

Re: Epiphany FPGA communication.

PostPosted: Tue Sep 30, 2014 9:10 am
by aolofsson
You can't really move the memory space around, you'll need to live with the ranges defined in the zynq manual. For the Epiphany, this meant that we had to alias some of the addresses to enable bidirectional communication. Should also be in section 4.1 of parallella manual:
http://parallella.org/docs/parallella_manual.pdf

Example of ramapping code (line ~500)
https://github.com/parallella/parallell ... rallella.v

The Epiphany needs to write "East" so you will likely need to do something like what was done above.

Andreas

Re: Epiphany FPGA communication.

PostPosted: Tue Sep 30, 2014 9:23 am
by AndyC
Thanks Andreas, I will take a look....

Re: Epiphany FPGA communication.

PostPosted: Mon Nov 24, 2014 2:13 pm
by Melkhior

Re: Epiphany FPGA communication.

PostPosted: Mon Nov 24, 2014 2:55 pm
by AndyC
Hi,

No I had no success, I couldn't get it to work and gave up hoping that something may be available in the new version to make this easier.

I would be interested in hearing if you get it to work though.

Cheers

Andy

Re: Epiphany FPGA communication.

PostPosted: Mon Nov 24, 2014 3:37 pm
by Melkhior