When using EMIO do I need to rebuild the FSBL
Posted: Thu Mar 30, 2017 1:31 pm
Hi all,
Not sure if the questions belongs here, but is is closely related to HW design. I've added SPI0 in the MIO configuration, io is routed through EMIO to a component in the PL (and from there to the outside world). Xilinx issue 47511 taken into account. Question is if I use EMIO do I need to rebuild the FSBL? (Or maybe in general do I always need to rebuild the FSBL if the configuration is changed?)
Thanks.
Not sure if the questions belongs here, but is is closely related to HW design. I've added SPI0 in the MIO configuration, io is routed through EMIO to a component in the PL (and from there to the outside world). Xilinx issue 47511 taken into account. Question is if I use EMIO do I need to rebuild the FSBL? (Or maybe in general do I always need to rebuild the FSBL if the configuration is changed?)
Thanks.