by theover » Sun Sep 13, 2015 10:24 pm
If I would have (or make) the time for it, I could make some actual examples that make clear what my interest is in putting these kinds of block structures onto processing threads on the Adapteva cores.
First though, I will try to explain a major reason for wanting some better interactions between the ARM cores and the FPGA and preferably the possibility to mingle in the communication between the Epiphany and the ARM, by intercepting messages in the FPGA, or at least being able to know at which time which message is being passed from the AXI to the external pins of the Zynq chip.
For making timed computations like in audio, and keeping the possibility for short sample count interactions between audio streams, it will be beneficial to be able to time, and schedule messages or activity with much greater accuracy than the buses in use at the moment easily allow. So if I'd take a simple timer FPGA circuit, consisting of a clock input connected to one of the phases of the 600 MHz clock, connected to a counter with an enable input freely usable from various clocking/message-ready signals, and a "one shot" possibility meaning that the counter will count one time from enable to end of enable, and not after that unless it's reset. I could measure the various phase relations and absolute service times that are present in the current FPGA + connections, memory access and Epiphany activity.
A similar circuit can be used to not measure, but with the best available accuracy schedule activities in the FPGA and the ARMs and the Epiphany. This setup is within the FPGA in most cases a strict and absolute schedule making possibility, which isn't at the moment the case when data runs over all kinds of loosely times interfaces, competition for memory access and unclear Epiphany synchronization patterns. Starting from a correct functional-type graph, it is possible with this setup to work on tight and timing accurate machine designs, without leaving anything to chance, which I'd prefer.
T.V.