8Gbps low latency chip to chip

[theover]

Hi all, or should I say Andreas,

I surfingly came accross this blog post about a fast interface:



I"ve looked at it a bit and saw there is a simulation and so on, but is it possible to try to use this interface with the 7010 board in practice ? Or would it require supercooling ?!

I mean I've not gone over all the memory mapped control fields to see if they are simular to the standard IF or looked at the verlog interface code to see if there are implementation parts there for the Zynq at hand, but it would be very nice if such speed (like suggested when the project started) would be available to work with a bit !

Theo V.

[sebraa]

To me, this reads like "we changed the FPGA logic and now it works better", so I guess it is just to be patient. The eLink interface used to be very small, so I assume the update will come to the Parallellas eventually. I hope.