Documentation Errors

[mrgs]

Hi ysapir, Oops... You are right. I've got it with a little support for me:
_DESCRIPTOR0;
.word 0x0000_0003; [NXT_PTR]_[DMACONFIG]
.word 0x0001_0001; [STRIDE-INNER-DST]_[STRIDE-INNER-SRC]
.word 0x0001_0008; [CNT-OUTER]_[CNT-INNER]
.word 0x0000_0000; [STRIDE-OUTER-DST]_[STRIDE-OUTER-SRC]
.word 0x0000_2000; [SRC_ADDRESS_HI]_[SRC_ADDRESS_LO]
.word 0x9200_0000; [DST_ADDRESS_HI]_[DST_ADDRESS_LO]
- Use DMA descriptor 'structure' rather than direct DMA register usage (It was just for 'understanding size' and meaning). OK. I got it.
- And start via 'movts DMACONFIG, R1'. OK. I got it earlier.
- I am going to use # prefix. ("mov R3, #0xF0F0; movt R3, #0xF0F0")
SUMMARIZE : Thank You for Your clarifying. Regards, Gabor

[timpart]

Architecture Ref 3.12.12.18 again

FLAGS
p46 AZ AN AV say unnaffected by non integer transactions. p 47 BZ BN BV say they are unaffected by non-floating point instructions. The secondary signed integer instructions are "floating point" in that they affect the B flags. but this isn't made clear. The B flag descriptions are in terms of genuine floating point.

Tables 16 on page 55 Why is AVS mentioned for instructions other than ADD and SUB? AV is set to zero for these so AVS cannot change.

Table 18 on page 57 mentions flags BN BZ BV BIS BVS BUS updated for IADD. Should BIS be removed? What situation is invalid? Should BUS be removed? How does underflow happen for integers? On page 96 IADD only mentions BN BV BZ BVS. This seems correct to me and the table wrong.
On page 97 IMADD includes BIS what circumstances set it? IMSUB doesn't have it. BV is present so why not BVS as well?

p98, 99 IMSUB, IMUL don't mention BVS, but change BV.

p100 ISUB mentions all 6 flags. Surely this is excessive? IMSUB sets fewer but does more.

p78, p119 ADD and SUB refer to setting OV, This should be AV. (Especially since the AVS formula refers to AV.)

STALLING
Could we have some more clarity about table 27 on page 68 please. Other tables preceding this one mention separations of instruction sequences and stalling if this isn't done.

Does the core stall in all the circumstances mentioned in table 27 without any possibility of doing useful work? I can imagine it would have to for the external instruction fetch, but the others might not need to. Elsewhere external data load is mentioned as disabling interrupts while it happens but can instructions that don't involve the register being fetched into continue in the meantime? More easily when a byte or halfword is being loaded internally can other instructions be done in the extra 2 cycle gap?

Thanks,

Tim

[timpart]

Architecture Ref 3.12.12.18

Just been reading the introduction again. On page 10 the first bullet says A superscalar, floating-point RISC CPU in each mesh node that can execute two floating point operations and a 64-bit memory load operation on every clock cycle

Can the chip really do two FLOPS per clock cycle? Nothing in the rest of the document suggest it an do more than one.

On page 11 it says up to 4096 nodes are supported. On page 18 it says 4095. I tend to agree with the latter as node 0,0 has ambiguity over its memory addresses.

Also on pages 113,114 can we have a reference to the possible values of <SPECIAL> ? E.g. CONFIG (see 7.5) STATUS (see 7.6) etc and a reference to Appendix B perhaps.

Thanks,

Tim

[aolofsson]

[timpart]

Thanks Andreas. I'm now aware of another "industry standard practice"!

In the absence of any comment to the contrary, I assume it is possible to change the chip mode from floating point to secondary integer and vice versa without having to wait for in progress operations to complete? So it is OK to have a mixture of these in the processing pipeline? (I presume the mode at the start of the processing is copied down the pipeline along with the data.)

The manual does say that there is a delay between doing a floating point (secondary integer) instruction and a special move using the same register, but that is a different concept.

Thanks,

Tim

[aolofsson]

Hi Tim,
Switching back and forth between integer and floating point for the secondary datapath has a pretty high overhead. Our assumption was that for most applications, the data plan would need either floating point or integer at any one time,so this wouldn't be a big deal. Hopefully that wasn't a bad assumption. (Pointer and control calculations is always handled by the regular integer datapath.)
Best regards,
Andreas

[timpart]

Well Andreas, the signed integer multiply is very tempting as the regular integer set has no multiplication. I suppose apart from that there isn't much call for it when working with a mix of integers and FP.

Since there is no unsigned multiply add, I guess the C compiler would do a sequence of shifts and adds to do arbitrary access to a 2D array. (Access within a loop is no problem since it can be done as an addition in each iteration.)

Hopefully the C compiler knows about the overhead. (Is it 4 cycles?) Does it assume the processor is in one of the modes all the time, and temporarily switch to the other one? Otherwise libraries involving floating point would have to assume nothing and switch every time they are called. I didn't notice anything in the application binary interface (EABI) about this.

Tim

[Janos]

Parallella Reference Manual 4.12.2.13

Page 7
1 Overview.
Table 1 Parallella Feature Summary

Coprocessor
The Parallella-64 board includes the 64-cire Epiphany-IV processor
The Parallella-64 board includes the 64-core Epiphany-IV processor

[Hoernchen]

Architecture Ref 3.12.12.18
p119
The description for SUB mentions SIMM8, this should be SIMM11.

[timpart]

Architecture Ref 3.12.12.18

P35 would it be better to refer to Xor and Or, i.e not all capitals? The assembler names are EOR and ORR.
P45 in table 11 would BV be better described as Floating-Point Overflow Flag? BVS isn't called Sticky Alternate...
P48 first paragraph Instructions-set should be Instruction-set. Also in the bulleted section instruction-set is spelt without hyphen.
P50 bottom floting-point should be floating-point.
P65 The instruction group list omits fabs from the FPU category. Is that deliberate or accidental? FABS, IADD and ISUB potentially could be much quicker than the other float instructions. Do they take the full floating point pipeline to be executed or do they come out early at E1 perhaps?
P85 Perhaps say Exclusive Ors rather than XORs.
P87 to 93 UbiasedExponent should be UnbiasedExponent.