Parallella Community

How can we build PCIe Parallella?
Is it like this?

PCIe------FPGA(that has Gbps tranceiver, and cheap one)-------Epiphany

ex. EP4CGX15BF14C8N : $25 on digikey

Morgaine.

You did not get the irony that you state that Stackable are not used on this Planet and we have them flying in space. They are, correctly, not serviced in space as conformal coated, sealed and wrapped up, etc.

Samtec are the manufactures of the connectors used on Parallella and the PC/104 Express uses similar connector. The PC/104 were DIN look-alike original, like 20 years ago. I recall a cycle-count of 1000 for Samtec's Q connectors - and why would anybody need to remove a Module more than that?? If you insist, then I will find the report in my pile in the office.

You do not like 'Stackable'... - fine! - but millions of Embedded Systems does. That is my point and my reason to enter this discussions as I believe you are wrong in this respect.

Back to Parallella, then - The Parallella choice of expansion via high-density connectors was the only choice, as so many I/O pins are available and I am confident that carriers boards will be developed and supported in the future. It gives Parallella the scalability we want for Multiprocessing.

Also, unlike is will change, so learn to endorse it.

Because I'm a software guy, so I don't know much about hardware, but, I think my is a sort of virtualization of gpu-cpu bus using Ethernet, it runs with sufficient performance even with 100Mbps NIC.

Ken Kutaragi said, "The network will become the peer-to-peer computing bus.", when he made the Cell/B.E.

I think that it would be nice if chips talk IPv6 directly instead of bus protocol, and using photon instead of electron. (means silicon photonics)

Then there is no need to spend logics for Bus-IP conversion, and we can connect chips to the other side of the planet earth easily.

I'm not kidding.

People will laugh at me, but it may become standard in the future.

I am not talking about just a network interface chip.
This is for any chips.
On this architecture, we can assign local/global IP address to phisical memory/IO address.
Isn't it exciting?