Hi,
I'm a new Parallella player. I had your project from Github > Opened in Vivado > Manually import constrains and sources into (The files were in project folder but not showed up on Vivado) > I hit Run behavior Sim and I had this problem:
ERROR: [VRFC 10-2063] Module <elink2_top> not found while processing module instance <elink2_top_i> [C:/Users/Kien/Desktop/parallella-fpga-abc1d5671a7cd59e706661a582075c0815de5ee7/7010_hdmi/7010_hdmi.srcs/sources_1/bd/elink2_top/hdl/elink2_top_wrapper.v:180]
ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed.
Here is my project structure: https://www.mediafire.com/?ed44m8dj2hzdtqn
I'm not sure what went wrong. Would you help me with this please? Thank you for your time.
Best
Kien