Parallella Community

Hi Guys,

When trying to build the bitstream from HDMI 7020 I get :

Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...
ERROR:EDK:3900 - issued from TCL procedure "zynqconfig_do" line 34
processing_system7_0 (processing_system7) - MHS file editing for Zynq related
parameters is not allowed. Please use Zynq tab in XPS for PS configuration.
Value of parameter C_FCLK_CLK1_FREQ (142857136) in MHS conflicts with the
setting in Zynq tab. Value of C_FCLK_CLK1_FREQ should be 142857152
ERROR:EDK:440 - platgen failed with errors!
make: *** [implementation/system_processing_system7_0_wrapper.ngc] Error 2
ERROR:EDK -
Error while running "make -f system.make netlist".
ERROR: [Edk 24-166] (generate_target): Failed to execute XPS script. Please check for any errors reported by the XPS application in the console: [C:/development/parallella-hw/fpga/edk/parallella_7020_hdmi/__xps/pa/_system_synth.tcl]


I have tried this with PlanAhead on linux and windows and get the same problem.

Anyone any ideas?

Cheers

Andy

Hi Andy,

I assume you've grabbed the current build files from github, and preserved all the hierarchy, then followed the directions to pull the HDMI design from the ADI repository (step 1 of the readme file in the project directory).

As a test, are you able to build the headless design? If so I'm wondering if ADI's design has moved to Vivado and might no longer work with PlanAhead, though I thought the way I referred to the ADI repository it should always grab the same revision so we should be protected from that sort of thing. I'll give it a try from a fresh checkout and see if I can still build or not.

Hi Fred,

Thanks for the reply.

Yep I followed all the steps correctly I think, it actually worked a week or so ago and then I deleted the files and started again from git and it failed. I retried a couple of times.

The headless design builds absolutely fine.

OK, I think it has to be something to do with the ADI/HDMI repository then, since nothing has changed in our repo in quite a while. I'll take a look, thanks for reporting the issue!

Hi,
I had a similar problem. I was using Debian testing 64bit with German locales.
In my case it was the first clock. XPS could not adjust the first clock (100MHz) to a better value than 102MHz and the synthesis complained with the same error. The problem was the input clock of 33.3333MHz was only calculated as 33.0 MHz. This was becasue of the German locales, where the decimal point is a comma. The commands unset LANG and unset LANGUAGE solved that problem for me...
now it seems to be synthesizing... still waiting.

I tried from a fresh checkout including pulling all the ADI/HDMI files, no problems.

ESI makes a good point about the locale settiing, I remember that thread but can't find it now. However I think that would make a much larger error, if I change from 33.333333MHz to 33MHz in XPS it causes a much larger change than you're seeing. Strangely, I can't get either of the values from your error message. If I open the XPS project from the repo that frequency is reported as 142.857132, trimming one '3' off the input frequency changes it to 142.857117, below the numbers in question are 142.857136 and 142.857152. Here is a capture of the clock settings from XPS when I open the project straight from the git repo:

XPS clock settings for HDMI project.

xps-clocks.png (88.96 KiB) Viewed 19578 times

If you open xps (either directly or by double-clicking on the system_i module in planAhead's project manager, then click on the "clock generation" block in the diagram, do you get the same values I show? If you then click on "Verify clocks" is it OK? Maybe this will help.

One more semi-random thing I can think of, if you go to the "Bus Interfaces" tab in XPS, what is the version number reported for the clock generator? I have 4.03.a, which is pre-production, but I don't see any updates available for it.

Sorry you're having trouble.