I just installed Vivado 2014.3.1just for the occasion, so that I have the build environment of the recipe from this page:
https://www.parallella.org/2015/03/23/n ... in-vivado/I got the zip file as described, opened in in Vivado, changed the target into the Zynq 7010 (which I have), did Tools-->Report-->reportipstatus "update All", opened the block diagram for e_link_top_i (double click in the "sources" window, double clicked on the parallella_gpio_emio_0 block, changed the number of GPIO's to 12 [11..0], clicked the GPIO_P and _N pins to reflect the same change, edited
./parallella_7020_headless_gpiose_elink2/parallella_7020_headless_gpiose_elink2.ipdefs/src/gpio/hdl/parallella_gpio_emio.v
and changed NUM_GPIO_PAIRS to 12, then refreshed the hierarchy and pressed Synthesize, Implement and Generate bitstream. There was an error about a block ram initialization compatibility problem, and the mentioned timing problems, but all runs to success (took about 2 minutes, on non-SSD drive).
Got the fake .elf file (from the git location mentioned at the bottom of the above page in a comment), created the bit2bin.bif file, and then was stuck, because the command "bootgen" simply isn't available in the this Vivado distribution. Luckily I found one in Vivado 2013.4, so I used that one to create the bit.bin file. I put the file (name changed properly to parallella.bit.bin) in the /boot of the SD card with the latest Linux, booted up and: it worked. I only tested e-bandwith and e-led, and some user ports, but everything functions. In fact , the resulting .bit file compares (using "cmp") as the same as the supplied .bit file, except it is 4 bytes smaller.
T.V.