Hi all,
I've, a while ago, looked at including silicon compilation from C code to bit file with Linux driving, with (limited) success, see here:
"Xilinx Webpack 2015.4 HLx edition".
Now the other day I downloaded the latest (no licence!) Webpack Vivado on my fast machine (it includes an amount of multi threading and caching of intermediate results it seems), tried to upgrade some test project I had, which worked without checking the bitfile, and looked at some more C examples, hoping for a better way to automatically create the AXI interface from the results of vivado_hl and maybe finding it could create some Linux side C driver programs.
Now, the examples on the design computer run fine, the C code versus VHDL simulator results works and matches, and maybe there are more examples this time (I don't recall) like streaming and some matrix examples. But, Apart from my own solution I mentioned in the thread I quoted above, there's certainly not an automated path I can find that lets the FPGA talk with a C program on the Zynq ARM in an easy way.
Does anybody know more about this?
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