Vivido project for parallella
Posted:
Fri Aug 12, 2016 9:26 am
by jimmystone
Hi, All
I find there is only one vivado project for parallella in
However, most design of this project is make with IPs, and cannot be changed by its verilog code.
And I notice the source code of elink is move to
Is there any vivado project works with these oh source code?
Or I need build one on my own?
Thanks.
Re: Vivido project for parallella
Posted:
Fri Aug 12, 2016 5:49 pm
by peteasa
oh is the one! If you follow the build instructions then it will create a vivado project and an fpga with the latest elink.. good luck!
Peter
Re: Vivido project for parallella
Posted:
Sun Aug 14, 2016 5:42 pm
by peteasa
I have found that xilinx modify the tcl interface quite a lot between versions. Worth a go to try the upgrade to 2016.2 but dont expect things to go smoothly. Easiest is to download 2015.2 plus the update. They will install ok so that you can use both at the same time, then build the oh fpga and stick with 2015.2. If you want to upgrade I am guessing that the easiest is to load the created project into 2016.2 and do the update that way. By update of the project you avoid the tcl issues. I would only update if you want a specific feature of 2016.2.
Peter.
Re: Vivido project for parallella
Posted:
Mon Aug 15, 2016 8:48 pm
by peteasa
@jimmystone: looks like the stable branch
https://github.com/parallella/oh/tree/stable is the best bet. I created a working project from that just now.
Peter.