Parallella Community

If you simply replaced the provided FPGA bitstream with your own that doesn't implement the glue logic required for ARM <-> Epiphany communication, I believe that the error is expected. Or maybe it has to do with memory zones.

What were the exact steps you followed to add your accelerator after opening the Parallella Vivado project?

Does your accelerator work if you replace the FPGA bitstream at runtime (dd if=bitstream.bit.bin of=/dev/xdevcfg)?
You need the Xilinx driver for doing so, so if you don't have it, you may need to build your own kernel.

I always boot with the original Epiphany bitstream, and then replace the FPGA logic at runtime (writing it to /dev/xdevcfg). This way, I can check (or unload) the Epiphany driver before loading my accelerator, which avoids a crash (my bitstreams do not contain the eLink interface, so the Epiphany driver must not be loaded).

Loading at runtime seems to reconfigure the FCLK clock speed, although I haven't tested this to be sure.

I do also boot with the original bitstream and replace with my own at runtime. However, simply loading the bitstream won't change your FCLKs, you need to do it explicitly before replacing the bitstream with your own (like the thread you reference mentions).

To achieve what you want, I would also ask over at Xilinx forums as this is not a question specific to Parallella.

But if I were you, I would simply write a script that executed as soon as Linux finishes booting and replaces the original bitstream with your own and changes clocks accordingly. From what I gather, you would obtain equivalent functionality

Hi, All

Update!
I can make my accelerator work at fclk3=35MHz, If I setting fclk3 above this freq, system will reboot.
I think there maybe power issue on Parallella.

Is there any way make a better power for Parallella?
Thanks.