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Xilinx Design Constraint

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Xilinx Design Constraint

PostPosted: Wed May 16, 2018 4:16 pm
by parallella-project
Hi,
As I've found various version of design constraint in github I am curious which one is exactly the right XDC for Parallella 7020?

Re: Xilinx Design Constraint

PostPosted: Thu May 17, 2018 9:17 am
by olajep
I/O pins
https://github.com/parallella/oh/blob/m ... lla_io.xdc

Additional z7020 "Parallella Embedded P1602 / Kickstarter" GPIO pins
https://github.com/parallella/oh/blob/m ... 020_io.xdc

Timings:
https://github.com/parallella/oh/blob/m ... timing.xdc


HTH,
Ola