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I walked through this patent that looks like 10 yo :
there are no specific data about inner epiphany router that manage a 2d mesh, and even if I can have that i may be not able to read / understand, so may be a good task for student :
Is it worth to extend epiphany mesh in a 3d space ?

I'm thinking of a group of 4 core per layer (5mmx5mm) and i hope that 1 chip may be under 1 mm width to reach from 10s to maybe 100s layer in a sodimm size connector with 4 way

This stack of cores may be cost very less because of small size and big amount and may be included in connector between peripherals.

For a very raw graphical concept of the connector you can find my channel in youtube.

Thanks for your time and for any helpful continuation of this post.

Cheers

Yes, maybe it's possible with a future design, but has additional engineering challenges.

Funny story...A couple years ago, at ISCA'15 Many-core Embedded Systems (MES) workshop,I presented the paper . I didn't write it. The researcher who did write it wasn't able to get a visa to present the paper.

The technique is in the title: multiplexed through-silicon vias

If you don't multiplex, the number of TSVs is high and the probability of a fabrication problem increases.

You may run into thermal problems with many layers. The Epiphany cores have higher power density than stacked DRAM.

Thanks for reply, I'm not talking about tsv, i'm talking about a mechanical stack as a double side bga or some pin that act as male and female will be better if possible.
I'm still curios if 25mm^2 may be enough to have 4 core + routers and multiplexers inside 1 chip and I wasn't able to get an idea on the height that is possible to reach, i hope in something like 0.1 / 0.5 mm if so is possible than all chips will be hold and cooled by a grid/cage of copper that will act as a farady cage around chips too ... like this it should be possible to make them now without "too much" engineer challenges in my mind.

If the heat it stills a problem it's possible to down-clock the core and make them working 1/2 frequency or alternately or even less ... no ?

Now a day the sodimm connector can reach around 200 connector in ~7 cm so 4 *200 are 800 cores and may be designed in copper or in optic fiber in the future (may be possible but I'm aiming to this )
so a block of 7 * 1.5 * 1.5 cm may contain enough resources for a portable device for example.

Sorry if I got too close to the moon I'm just pushing my thought as close as possible to the reality but I have not enough cognition of cause so if you find something useful in my words make it yours.

Looking for more connection between real world and my mind .
Thanks in advance for your replies

A

I think the E5 architecture includes provision for arrangement in a 3D grid: the scratchpad addresses split the bits into x/y/z coordinates, instead of just 2d coords as in the E3/E4.
https://www.parallella.org/wp-content/u ... re_soc.pdf
it mentions 30bits dedicated to x,y,z addressing, so I guess they imagine a logical 1024x1024x1024 cube (if anyone put in an order for a billion chips ..) EDIT: but they also want that for addressing memory pools, and of course real 3d stacked memory *does* exist.

I realise there are 2 things being discussed in this thread, 'real' 3d chips, and 3d topology connecting traditional chips.

I guess he was thinking ahead with the design. I suppose you could have stacked boards? and is there future potential for silicon-photonics to stretch the topology further?

I suppose if you had companion chips or FPGAs doing advanced routing you could have shortcuts in the topology between chips? e.g. imagine coiling up the dimensions so 2d is actually implemented as 4d, think of presenting a 4d array as tiled slices in a 2d grid .. but I realise this thread is more about physical 3d. Don't some supercomputers have logical 6D topology or something..