HI,
Recently I've tested again running the planAhead (from Ise WebPack 14.7 IIRC) on the Parallella supplied sources (including the AD HDMI interface), changed some things (in this case about some of the GPIO pins), loaded in the new bit.bin file, and tested the result to work, which is fine.
However now I'd like to do a bit more communication with the FPGA pins than the GPIO allows, for instance by adding a simple ARM-FPGA link with registers (like the Xilinx software can generate), or possible by defining new messages or communication end-points in the existing ARM<->Epiphany link with fifos, word width adaptations and flow control.
Did anyone work on this or know by heart if it is possible to add a simple (like the Xilinx examples) interface to the existing ones, without breaking the alrready working system ?
Also, is it easy enough to follow the OS support for the Epiphany to add stuff or add an additional interface to the kernel device tree or something ?
Thanks,
Theo V.