by patc » Wed Nov 16, 2016 10:34 am
A tip some may find useful
The Vivado Integrated Logic Analyzer (ILA) is an outstanding tool but can be frustrating to operate. Many times I found myself in the situation where I placed debug marks on the synthesized schematic, set up debug core and got everything working fine but then after changing the design a bit to try out something else, I could get some constraint missing errors which sometimes could be solved by disconnecting completely the debug core and doing a setup again, but some other times I had to revert to a version without debug and restart from scratch (okay, still have tons to learn about Vivado).
Eventually my Good Star kicked in as I found out a method which works great:
- add an AXI_GPIO IP to the design and set the GPIO Width to the number of desired probes (All Inputs)
- mark the GPIO as Debug and Run Connection Automation to add and set a SYSTEM_ILA IP (picture #1)
- from the HDL wrapper, pass the gpio_rtl_tri_i to the desired module to debug (picture #2)
- connect to the signals to analyze (picture #2)
- debug (picture #3)
- make changes and re-generate without having to worry any longer about mismatch hassles
- solve the problem in no time and go sip a beer!
More generally, if possible, try to isolate the problem and make the design as small as possible so that it doesn't take too much time to build.
I suppose this method is described somewhere because the Run Connection Automation is setting ILA properly.
For the story, I had 4 sources outputting with different SPDIF interfaces 24-bit @88200 to a Zynq emio set as spdif input. 3 sources were working flawlessly but I got only garbage from the fourth one. Yet when this source was connected to some other equipments, everything was perfect so it had to be something in the vhdl code. For this kind of problem it's necessary to take a close look deep down at the real time data and I find the ILA "best of the class".
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- pict2.jpg (110.42 KiB) Viewed 45662 times
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- pict3.jpg (86.73 KiB) Viewed 45662 times