Okay, I had a quick look at a diff of a good working project versus what I got on a fresh project.
It seems on both my AXI4Lite and AXI4 projects, I am using the other bus interface, which is not enabled by default. That is, M_AXI_GP0 rather than M_AXI_GP1.
The difference in the system.mhs which I think is relevant is:
< BUS_INTERFACE M_AXI_GP1 = axi_interconnect_1
---
> PARAMETER C_USE_M_AXI_GP0 = 1
> BUS_INTERFACE M_AXI_GP0 = axi_interconnect_1
I spent some time comparing the XPS sources between Parallella and Zedboard working that one out. I can't remember why I concluded this was needed.
I don't like giving directions without testing them myself, but it is late and I think there is a good chance this may sort you out. Good luck, and I will definitely get to the bottom of it tomorrow if this does not resolve it for you

You can implement these changes by just editing your file (easiest) - or you can double click 32b GP AXI Master Ports at the lower left of the system diagram (The one on the Zynq tab in XPS) and enable GP0, then go to the Bus Interfaces tab and assign axi_interconnect_1 to M_AXI_GP0.