I ported the accelerator to Vivado 2017.2. Looks like this version is a bit more picky about missing wires etc., needed some fixed in OH components. These are the differences:
https://github.com/FrankBuss/oh/commit/ ... 807ceceefbThe system_bd.tcl file was just re-created by Vivado as suggested from the script, with "write_bd_tcl" on the Tcl command line. I guess it would be as easy with the parallella project.
BTW, I noticed the OH components are very unfinished, like there is a lot of empty modules and skeleton code. Is this project still alive and do people write code for it? Personally I don't like Verilog, I prefer VHDL. But recently I discovered Chisel ( ), which makes it much easier to write HDL programs, because it has the power of Scala as the backend. For example exhaustive testbenches are much simpler to write and run. Or need a ROM with a sin-table? No problem with a real language like Scala, just one line to generate it inline for the synthesizing step. This might be a better base for the OH framework.