Ideas for daughter cards?

[shodruk]

Mark,
Yes, samtec connectors are very expensive.
But I think we can use BSH-120 instead of 4x BSH-030 to save some money.

BSH-120 $9.66
http://www.digikey.com/product-detail/e ... ND/1975817
BTH-120 $9.86
http://www.digikey.com/product-detail/e ... ND/1975824
--------------
$19.52 per add-on board

BSH-030 $5.89
http://www.digikey.com/product-detail/e ... ND/2619990
BTH-030 $6.00(maybe)
x4
--------------
$47.56 per add-on board


Andrew,
Thanks! The third eLink would be very useful.


Tim,
Yes, we can add the Epiphany on Parallella to the eLink network, but I thought that implementing eLink router on FPGA can be a nightmare, so I thought it's better to let it isolate.


Andreas,
Great! I expect that doubles something...

[shodruk]

Epiphany SO-DIMM module inspired by

epidimm.png (44.31 KiB) Viewed 55859 times

[aolofsson]

Nice

Using the SODIMM concept is well known and there are quite a few boards out there already with this form factor. Here's one from Switzerland that uses the Zynq:

http://www.enclustra.com/en/products/fp ... /mars-ax3/

Not sure if this is our highest priority, but the Parallella is open source so if there is a market for this type of SODIMM I am sure somebody will build one.

Andreas

[ralsalamanca]

A HDMI input

[parapara]

[parapara]

on the rev0 pages you said that the overheating is caused by a linear 1.8V regulator
+ unecessarily high IO voltage for the epiphany.

Would it work to create an addon board with a better regulator? (that would solve the 1.8V power amplification)
Is there something that prevents such rev0-fix daughterboard from shutting that regulator down and providing 1.8V instead?

[parapara]

+1 for the additional ethernet expansion.

I do have a question about that, though.
Earlier it was said that the 2nd GLan controller is unavailable.
By the Zynq docs, even though there aren't enough PS pins for some of the peripherals
it should still be possible to access remaining features from the FPGA side and route them to fpga pins instead.
Sounds bulletproof to me.
What did I miss?

[aolofsson]

Yes, we can route the ethernet port through the programmable logic to the GPIO expansion connector...but someone still needs to build an expansion board with a PHY and rj45.
Andreas

[9600]

[parapara]

I wonder why do you ask only about the PL part.
Is the required modification of the PS side / device tree obvious?

I'm glad you like the idea.
What do you think about providing/shipping the required changes by default?
(OR, if the power consumption impact turns out to be noticeable, prepared and commented out?)
Availability of the second (R?)GMII could be a good incentive for overcoming the Samtec-sourcing hurdle.

Remark from the table "MIO Peripheral Interface Mapping" - row "GigE: 0,1"
While for regular PS pins "MIO" it mandates RGMII v2.0, External PHY
For PL "EMIO" it seems to offer way more options:
. . . GMII, RGMII v2.0 (HSTL), RGMII v1.3, MII, SGMII,
. . . and 1000BASE-X in Programmable Logic
However, the figure directly after the table lits only "GMII" for the EMIO interconnection.
I assume that just implies that one can implement a PHY or other xGMII-s in PL if she desires to?
Given the already existing trouble with heat, a dedicated PHY seems like a good idea anyway.

I'd definitely like to hear back about the required changes,
but it seems a bit off topic here. Is a good idea to create a separate topic?